This invention is in the field of motor control, and is more specifically directed to control of voice coil motors as used in computer disk drive controllers.
As is evident in the industry, the magnetic disk drive remains the dominant technology for mass read/write storage in modem computers, including both desktop workstations and also portable “laptop” computers. Magnetic disk drives are now also popular in smaller scale portable systems, such as portable audio systems and players.
Modern disk drives typically include a “spindle” motor and a “voice coil” motor. The spindle motor spins the magnetic disks during operation, so that sectors at a given radius of the disk pass by the data transducer, or read/write “head”. The voice coil motor positions the data transducer at the radial positions of the magnetic disk surface that correspond to the track locations to which data are being written or from which data are being read. Typically, the data transducer is at the end of a positioning arm that pivots across the surface of the spinning magnetic disk, from a pivot point outside of the circumference of the magnetic disk, so that pivoting of the positioning arm changes the radial position of the data transducer over the magnetic disk surface. The voice coil motor controls the pivoting of the positioning arm, and thus the track location of the data transducer.
Voice coil motor controller circuitry generally provides drive signals to the voice coil motor through a pair of output drivers, typically including high-side and low-side drivers connected on opposite sides of the voice coil motor. In operation, the positioning arm is pivoted in one direction by the high side driver sourcing current through the voice coil motor to the low side driver, and pivoted in the opposite direction by the low side driver source current through the voice coil motor to the high side driver.
By way of further background, U.S. Pat. No. 5,838,515 describes a dual mode voice coil motor driver that operates in a pulse-width-modulated (“Class D”) mode and also in a linear mode. As well known in the art, the “track following” operating mode of the voice coil motor maintains the data transducer at a desired track location, and the “track seek” operating mode moves the positioning arm from one track location to another. This reference describes that the voice coil motor operates in a pulse-width-modulated mode during track seek, but is placed into the linear mode at the onset of a deceleration phase of the seek trajectory, staying in linear mode during track following.
Referring now to FIG. 1, a conventional pulse-width-modulated voice coil motor driver is illustrated. In this example, a differential error signal is received on lines ERRP, ERRM. Input line ERRP is applied to the non-inverting input of comparator 3H, and input line ERRM is applied to the non-inverting input of comparator 3L. The differential error signal on lines ERRP, ERRM is generally developed by an error amplifier (not shown) that compares a feedback signal with a desired input level. Ramp clock generator 2 generates a triangle wave signal, at a frequency corresponding to that of the desired pulse-width-modulated (PWM) output signal, and applies this ramp clock signal to the inverting inputs of comparators 3H, 3L. The output of comparator 3H is applied to the input of differential PWM output amplifier 4H, and the output of comparator 3L is connected to the input of differential PWM output amplifier 4L. Differential PWM output amplifier 4H generates output levels that are applied to the gates of power transistors 5PH, 5PL, and that define a differential voltage gP; similarly, differential PWM output amplifier 4L generates output levels that are applied to the gates of power transistors 5NH, 5NL, at a differential voltage gM.
Power transistors 5 are arranged in the conventional “H” bridge, as known in the art for powering voice coil motor (VCM) 9. In this arrangement, power transistors 5PH, 5PL have their source-drain paths connected in series between power supply voltage VM and ground, as do power transistors 5NH, 5NL. VCM 9 is connected between node VCMP at the drain of transistor 5PL and the source of transistor 5PH (transistors 5PL, 5PH each being n-channel devices in this example), and node VCMN at the drain of transistor 5NL and the source of transistor 5NH. Accordingly, the relative voltages at nodes VCMP, VCMN determine the polarity and magnitude of current conducted through VCM 9.
The operation of the conventional arrangement of FIG. 1 will now be described relative to FIG. 2. As evident from FIG. 2, the relationship between the signals on input error lines ERRP, ERRM, on one hand, and the output signal RMP from ramp clock generator 2, on the other hand, determines the current through VCM 9. As shown in FIG. 2, differential voltage gP from PWM output amplifier 4H is positive in response to the voltage on line ERRP being higher than the instantaneous voltage of ramp clock RMP, and is negative when line ERRP is at a lower voltage than that of ramp clock RMP. In this example, referring back to FIG. 1, a positive differential voltage gP turns on transistor 5PH relative to transistor 5PL, which pulls the voltage at node VCMP toward power supply voltage VM. Similarly, differential voltage gM from PWM output amplifier 4L is positive in response to the voltage on line ERRM being lower than the instantaneous voltage of ramp clock RMP, and is negative when line ERRM is at a higher voltage than that of ramp clock RMP. A positive differential voltage gM turns on transistor 5NL relative to transistor 5NH, which pulls the voltage at node VCMN toward ground.
In general, current is conducted between nodes VCMA, VCMB and through VCM 9 when the voltages at nodes VCMP, VCMN differ from one another. In FIG. 2, current pulses T0 through T3 illustrate positive polarity currents conducted through VCM 9, corresponding to those times at which both of differential voltages gP, gM are of positive polarity, and current pulses T4 and T5 illustrate negative polarity currents through VCM 9, corresponding to both of differential voltages gP, gM being negative polarity. In this example, positive polarity current pulses such as those in pulses T0 through T3 result from the situation in which the voltage at input line ERRP is above reference voltage Vref while the voltage at input line ERRM is below reference voltage Vref. Conversely, during those times at which input line ERRP is at a voltage lower than that of waveform RMP in combination with input line ERRM also at a voltage lower than that of waveform RMP, a current is conducted through VCM 9 in the opposite direction, as shown by current pulses T4, T5 and the corresponding differential voltages gP, gM. In the example of FIG. 2, this negative current drive is the result of the voltage of input line ERRP falling below reference voltage Vref and the voltage of input line ERRM rising above reference voltage Vref. During those times at which the differential voltages gP, gM are of opposite polarity, the voltages at nodes VCMP, VCMN are effectively equal to one another, and no current is conducted.
It has been observed, in connection with this invention, that variations in power supply voltage affect the transconductance, or open-loop, gain of the conventional PWM VCM drive circuit of FIG. 1, and will therefore affect the current driven through VCM 9. It is apparent from FIG. 1 that the current through power transistors 5 of the “H” bridge arrangement will depend directly on the power supply voltage VM; obviously, a higher power supply voltage VM will result in higher drain currents, and thus higher currents through VCM 9, for a given fixed duty cycle.
Referring to FIG. 2, one can consider reference voltage Vref as a “pseudo-ground” for purposes of considering the gain of the drive circuit. If the error voltages at lines ERRP, ERRM are both at reference voltage Vref, no current will be driven; this is the 0% duty cycle voltage. If the error voltages at lines ERRP, ERRM are at respective peak voltages of ramp clock RMP, current will be constantly driven through VCM 9. For example, if the error voltage at line ERRP is at the positive peak voltage while the error voltage at line ERRM is at the negative peak level, positive current will be driven through VCM 9 at a 100% duty cycle. Conversely, if the error voltage at line ERRP is at the negative peak voltage while the error voltage at line ERRM is at the positive peak level, negative current will be driven through VCM 9, also at a 100% duty cycle.
The effect of power supply variations can be considered by way of an example, in which power supply voltage VM is 12 volts, the open-loop gain of drive stage is nominally 12, and with reference voltage Vref at ground. Accordingly, the center-to-peak voltage Vpeak of the ramp clock RMP, at which 100% duty cycle is obtained, can be considered from:
                              V          peak                =                                            V              M                        gain                    =                                    12              12                        =                          1              ⁢                                                          ⁢              volt                                                          (        1        )            Because VCM 9 is a bidirectional motor, the peak-to-peak voltage ramp of ramp clock RMP in this situation will be 2 volts. But power supply voltage VM can vary from 10.8 to 13.2 volts, if a ±10% power supply voltage tolerance is specified. Maintaining the center-to-peak voltage Vpeak at 1 volt over this ±10% variation in power supply voltage VM, the drive circuit open-loop gain will correspondingly varies from 10.8 to 13.2. Variations in the power supply voltage VM thus cause corresponding variations in the open-loop gain.
The effect of these variations in open-loop gain are most evident in dual-mode voice coil motor driver circuits, such as described in U.S. Pat. No. 6,374,043, issued Apr. 16, 2002, assigned to Texas Instruments Incorporated and incorporated herein by this reference. In the linear mode, feedback control of the VCM drive will eliminate variations in the drive of power transistors 5. In addition, many class D or pulse-width-modulated voice coil motor drive systems or modes also include feedback control, that will compensate for variations in open-loop gain during steady-state operation in that mode. However, dual-mode voice coil motor driver circuits, such as described in U.S. Pat. No. 6,374,043, make transitions from the linear mode to the PWM mode. When making a transition, the open-loop gain of the drive circuit will dominate the drive of the voice coil motor until such time as the feedback control loop can respond to the resulting error. Accordingly, variations in open-loop gain, for example of the “H” bridge of power transistors 5 in FIG. 1, can be quite evident in transitions between drive modes.
In addition, some conventional disk drive systems do not use electrical feedback for control of the position of the data transducers, and thus for control of the voice coil motor, but instead use a mechanical positioning device for such control. In these conventional systems, variations in the open-loop gain of the voice coil motor drive circuit will directly affect the positioning of the data transducers. It is believed that these gain variations will lengthen the track settling times, and in severe cases may cause positioning errors.